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IEEE 1800-2023
IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language
NORMA vydaná dňa 28.2.2024
Informácie o norme:
Označenie normy: IEEE 1800-2023
Dátum vydania normy: 28.2.2024
Kód tovaru: NS-1168252
Počet strán: 1354
Približná hmotnosť: 4093 g (9.02 libier)
Krajina: Medzinárodná technická norma
Kategória: Technické normy IEEE
Anotácia textu normy IEEE 1800-2023 :
Revision Standard - Active.
The definition of the language syntax and semantics for SystemVerilog, which is a unified hardware design, specification, and verification language, is provided. This standard includes support for modeling hardware at the behavioral, register transfer level (RTL), and gate-level abstraction levels, and for writing test benches using coverage, assertions, object-oriented programming, and constrained random verification. The standard also provides application programming interfaces (APIs) to foreign programming languages. (The PDF of this standard is available at no cost at compliments of Accellera Systems Initiative)
ISBN: 979-8-8557-0501-0
Number of Pages: 1354
Product Code: STDPD26763
Keywords: assertions, design automation, design verification, hardware description language, HDL, HDVL, IEEE Std 1800™, PLI, programming language interface, SystemVerilog, Verilog®, VPI
Category: Design Automation
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