IEC 61523-1-ed.3.0

Anotácia textu normy IEC 61523-1-ed.3.0 :

IEC 61523-1:2023 focuses on delay and power calculation for integrated circuit design with support for modeling logical behavior and signal integrity. The standard specifications covered in this document are as follows: - Description language for timing and power modeling, called the “delay calculation language” (DCL) - Software procedural interface (PI) for communications between EDA applications and compiled libraries of DCL descriptions - Standard file exchange format for parasitic information about the chip design: Standard Parasitic Exchange Format (SPEF) - Informative usage examples - Informative notes. This is an IEC/IEEE dual logo standard.